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| PA7536 PEEL ArrayTM Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other wide-gate functions High-Speed Commercial and Industrial Versions - As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 C temperatures CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - Anachip WinPLACE Development Software - Fitters for ABEL and other software - Programming support by popular third-party programmers General Description The PA7536 is a member of the Programmable Electrically Erasable Logic (PEELTM) Array family based on ICT's CMOS EEPROM technology. PEELTM Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today's programmable logic designs. The PA7536 offers a versatile logic array architecture with 12 I/O pins, 14 input pins and 36 registers/latches (12 buried logic cells, 12 Input registers/latches and 12 buried registers/latches). Its logic array implements 50 sum-of-products logic functions that share 64 product terms. The PA7536's logic and I/O cells (LCCs, IOCs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells). Cells are configurable as D, T, and JK registers with independent or global clocks, resets, presets, clock polarity, and other special features, making the PA7536 suitable for a variety of combinatorial, synchronous and asynchronous logic applications. The PA7536 offers pin compatibility and super-set functionality to popular 28-pin PLDs, such as the 26V12. Thus, designs that exceed the architectures of such devices can be expanded upon. The PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (fMAX) at moderate power consumption 105mA (75mA typical). Packaging includes 28-pin DIP, SOIC, and PLCC (see Figure 1). Development and programming support for the PA7536 is provided by Anachip and popular third-party development tool manufacturers. Figure 1. Pin Configuration I/CLK1 I I I I I VCC I I I I I I I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/CLK2 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/CLK1 I I I I I VCC I I I I I I I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/CLK2 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O Figure 2. Block Diagram 2 Input/ Global Clock Pins Global Cells 76 (38X2) Array Inputs true and com plement 12 Buried logic Logic functions to I/O cells I/O Cells (IOC) 12 I/O Pins 12 Input Pins Input Cells (INC) 2 12 S O IC I/CLK1 I/CLK2 I/O I/O 12 I/CL K1 I I I In p ut C ells I I/O Ce lls G lo ba l Ce lls I/CL K2 I/O I/O I/O I/O I/O I/O G ND I/O I/O I/O L og ic Co ntro l C e lls I/O I/O I/O L og ic Array D IP 4 I I VCC I I I I 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 2 1 28 27 26 25 24 23 22 21 20 19 I/O I/O I/O I/O GND I/O I/O A B C D Logic Control Cells (LCC) I I I 12 12 I VC C I I I I I I I 08 -16 -0 01A 2 sum terms 3 product term s for Global Cells 48 sum term s (four per LCC) 12 Logic Control Cells up to 3 output functions per cell (36 total output functions possible) I I I I/O I/O I/O I/O PLCC P A7536 0 8-1 6-0 02 A 1 04-02-052A Inside the Logic Array The heart of the PEELTM Array architecture is based on a logic array structure similar to that of a PLA (programmable AND, programmable OR). The logic array implements all logic functions and provides interconnection and control of the cells. Depending on the PEELTM Array selected, a range of 38 to 62 inputs is available into the array from the I/O cells, inputs cells and input/global-clock pins. All inputs provide both true and complement signals, which can be programmed to any product term in the array. The number of product-terms among PEELTM Arrays ranges from 67 to 125. All product terms (with the exception of certain ones fed to the global cells) can be programmably connected to any of the sum-terms of the logic control cells (four sum-terms per logic control cell). Product-terms and sum-terms are also routed to the global cells for control purposes. Figure 3 shows a detailed view of the logic array structure. ensures that product-terms are used where they are needed and not left unutilized or duplicated. Secondly, the sum-of-products functions provided to the logic cells can be used for clocks, resets, presets and output enables instead of just simple product-term control. The PEELTM logic array can also implement logic functions with many product terms within a single-level delay. For example a 16-bit comparator needs 32 shared product terms to implement 16 exclusive-OR functions. The PEELTM logic array easily handles this in a single level delay. Other PLDs/CPLDs either run out of product-terms or require expanders or additional logic levels that often slow performance and skew timing. Logic Control Cell (LCC) Logic Control Cells (LCC) are used to allocate and control the logic functions created in the logic array. Each LCC has four primary inputs and three outputs. The inputs to each LCC are complete sum-of-product logic functions from the array, which can be used to implement combinatorial and sequential logic functions, and to control LCC registers and I/O cell output enables. From G lobal C ell System Clock Preset RegType Reset From IO C ells (IO C,INC, I/CLK) 38 Array Inputs O n/O ff MUX P D ,T,J Q From Logic Control Cells (LCC) To Array MUX K R EG R To G lobal Cells 67 Product T erm s From Array A B C D MUX To I/O Cell To Logic Control Cells (LCC) 08 -16-0 04A 08-16-003A Figure 4. Logic Control Cell Block Diagram As shown in Figure 4, the LCC is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous D, T, or JK registers (clocked-SR registers, which are a subset of JK, are also possible). See Figure 5. EEPROM memory cells are used for programming the desired configuration. Four sum-ofproduct logic functions (SUM terms A, B, C and D) are fed into each LCC from the logic array. Each SUM term can be selectively used for multiple functions as listed below. PA 7536 Logic Array 50 Sum Term s Figure 3 PA7536 Logic Array True Product-Term Sharing The PEELTM logic array provides several advantages over common PLD logic arrays. First, it allows for true productterm sharing, not simply product-term steering, as commonly found in other CPLDs. Product term sharing 2 04-02-052A Sum-A = D, T, J or Sum-A Sum-B = Preset, K or Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable, Sum-D D P D R e g is te r Q = D after clocked third, an output enable or an additional buried logic function. The multi-function PEELTM Array logic cells are equivalent to two or three macrocells of other PLDs, which have only one output per cell. They also allow registers to be truly buried from I/O pins without limiting them to inputonly (see Figure 8 and Figure 9). From Global Cell Input Cell Clock Q Best for storage, sim ple counters, shifters and state m achines with few hold (loop) conditions. R T P Q T R e g is te r Q toggles when T = 1 Q holds when T = 0 REG / Latch Q R Best for wide binary counters (saves product term s) and state m achines with m any hold (loop) conditions. Input P J K R e g is te r Q toggles when J/K = 1/1 Q holds when J/K = 0/0 Q=1 when J/K = 1/0 Q=0 when J/K = 0/1 M UX Input To Array Input Cell (INC) J K Q R Com bines features of both D and T registers. 08-16-005A From Global Cell Input Cell Clock REG / Latch Q Figure 5. LCC Register Types SUM-A can serve as the D, T, or J input of the register or a combinatorial path. SUM-B can serve as the K input, or the preset to the register, or a combinatorial path. SUM-C can be the clock, the reset to the register, or a combinatorial path. SUM-D can be the clock to the register, the output enable for the connected I/O cell, or an internal feedback node. Note that the sums controlling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other PLDs. This also means that any input or I/O pin can be used as a clock or other control function. Several signals from the global cell are provided primarily for synchronous (global) register control. The global cell signals are routed to all LCCs. These signals include a high-speed clock of positive or negative polarity, global preset and reset, and a special register-type control that selectively allows dynamic switching of register type. This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from D-type registers to load and T-type registers to count (see Figure 11). To Array Input M UX M UX From Logic Control Cell A,B,C or Q M UX I/O Pin M UX D 10 I/O Cell (IOC) 08-16-006A Figure 6. I/O Cell Block Diagram D Q IO C /IN C R e g is te r Q = D after rising edge of clock holds until next rising edge L Q IO C /IN C L a tc h Q = L when clock is high holds value when clock is low Multiple Outputs Per Logic Cell An important feature of the logic control cell is its capability to have multiple output functions per cell, each operating independently. As shown in Figure 4, two of the three outputs can select the Q output from the register or the Sum A, B or C combinatorial paths. Thus, one LCC output can be registered, one output can be combinatorial and the 3 08-16-007A Figure 7. IOC Register Configurations 04-02-052A Input Cells (INC) Input cells (INC) are included on dedicated input pins. The block diagram of the INC is shown in Figure 6. Each INC consists of a multiplexer and a register/transparent latch, which can be clocked from various sources selected by the global cell. The register is rising edge clocked. The latch is transparent when the clock is high and latched on the clock's failing edge. The register/latch can also be bypassed for a non registered input. Global Cells The global cells, shown in Figure 10, are used to direct global clock signals and/or control terms to the LCCs, IOCs and INCs. The global cells allow a clock to be selected from the CLK1 pin, CLK2 pin, or a product term from the logic array (PCLK). They also provide polarity control for IOC clocks enabling rising or falling clock edges for input registers/latches. Note that each individual LCC clock has its own polarity control. The global cell includes sum-ofproducts control terms for global reset and preset, and a fast product term control for LCC register-type, used to save product terms for loadable counters and state machines (see Figure 11). The PA7536 provides two global cells that divide the LCC and IOCs into two groups, A and B. Half of the LCCs and IOCs use global cell A, half use global cell B. This means, for instance, two high-speed global clocks can be used among the LCCs. CLK1 CLK2 M UX PCLK INC Clocks I/O Cell (IOC) All PEELTM Arrays have I/O cells (IOC) as shown above in Figure 6. Inputs to the IOCs can be fed from any of the LCCs in the array. Each IOC consists of routing and control multiplexers, an input register/transparent latch, a threestate buffer and an output polarity control. The register/ latch can be clocked from a variety of sources determined by the global cell. It can also be bypassed for a nonregistered input. A feature of the 7536 IOC is the use of SUM-D as a feed-back to the array when the I/O pin is a dedicated output. This allows for additional buried registers and logic paths. (See Figure 8 & Figure 9). Global C ell: IN C G roup A & B CLK1 Q D M UX LCC Clocks Input w ith optional register/latch CLK2 I/O M UX PCLK Reg-Type IO C Clocks LCC Reg-Typ e LCC Presets LCC Resets I/O w ith independent output enable A B C D DQ Preset Reset 1 2 OE 08-16-008A G lobal C ell: LC C & IO C 08-16-010A Figure 10. Global Cells Reg-Type from G lobal Cell Figure 8. LCC & IOC With Two Outputs R e g is te r T yp e C h a n g e F e a tu re Q D D P Q Buried register or logic paths O utput R G lobal Cell can dynam ically change userselected LCC registers from D to T or from D to JK. This saves product terms for loadable counters or sta te m achines. Use as D register to load, use as T or JK to count. Tim ing allo ws dynam ic opera tion. A B C D DQ 1 2 3 T 08-16-009A P E x a m p le : Product terms for 10 bit loadable binary co unter Q D uses 57 prod uct term s (47 count, 10 load ) T uses 30 prod uct term s (10 count, 20 load ) D/T uses 20 product term s (10 count, 10 lo ad) 08-16-011A R Figure 9. LCC & IOC With Three Outputs 4 Figure 11. Register Type Change Feature 04-02-052A PEELTM Array Development Support Development support for PEELTM Arrays is provided by Anachip and manufacturers of popular development tools. Anachip offers the powerful PLACE Development Software (free to qualified PLD designers). The PLACE software includes an architectural editor, logic compiler, waveform simulator, documentation utility and a programmer interface. The PLACE editor graphically illustrates and controls the PEELTM Array's architecture, making the overall design easy to understand, while allowing the effectiveness of boolean logic equations, state machine design and truth table entry. The PLACE compiler performs logic transformation and reduction, making it possible to specify equations in almost any fashion and fit the most logic possible in every design. PLACE also provides a multi-level logic simulator allowing external and internal signals to be simulated and analyzed via a waveform display.(See Figure 12, Figure 13 and Figure 14) waste. Programming of PEELTM Arrays is supported by popular third party programmers. Design Security and Signature Word The PEELTM Arrays provide a special EEPROM security bit that prevents unauthorized reading or copying of designs. Once set, the programmed bits of the PEELTM Arrays cannot be accessed until the entire chip has been electrically erased. Another programming feature, signature word, allows a user-definable code to be programmed into the PEELTM Array. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed in the device or to record the design revision. Figure 13 - PLACE LCC and IOC screen Figure 12 - PLACE Architectural Editor for PA7536 PEELTM Array development is also supported by popular development tools, such as ABEL and CUPL, via ICT's PEELTM Array fitters. A special smart translator utility adds the capability to directly convert JEDEC files for other devices into equivalent JEDEC files for pin-compatible PEELTM Arrays. Programming PEELTM Arrays are EE-reprogrammable in all package types, plastic-DIP, PLCC and SOIC. This makes them an ideal development vehicle for the lab. EEreprogrammability is also useful for production, allowing unexpected changes to be made quickly and without 5 Figure 14 - PLACE simulator screen 04-02-052A Table 1. Absolute Maximum Ratings Symbol VCC VI, VO IO TST TLT Parameter Supply Voltage Voltage Applied to Any Pin Output Current Storage Temperature Lead Temperature Conditions Relative to Ground Relative to Ground Per pin (IOL, IOH) Soldering 10 seconds 1 Ratings -0.5 to + 7.0 -0.5 to VCC + 0.6 25 -65 to + 150 +300 Unit V V mA C C Table 2. Operating Ranges Symbol VCC TA TR TF TRVCC Parameter Supply Voltage Ambient Temperature Clock Rise Time Clock Fall Time VCC Rise Time Conditions Commercial Industrial Commercial Industrial See Note 2 See Note 2 See Note 2 Min 4.75 4.5 0 -40 Max 5.25 5.5 +70 +85 20 20 250 Unit V C ns ns ms Table 3. D.C. Electrical Characteristics Symbol VOH VOHC VOL VOLC VIH VIL IIL IOZ ISC ICC11 CIN7 COUT7 Over the Operating Range Conditions Min 2.4 VCC - 0.3 0.5 0.15 2.0 -0.3 VCC + 0.3 0.8 10 10 -30 -15 45 (typ.)19 -120 70 6 Parameter Output HIGH Voltage - TTL Output HIGH Voltage CMOS Output LOW Voltage - TTL Output LOW Voltage CMOS Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current4 VCC Current Input Capacitance5 Output Capacitance5 Max Unit V V V V V V A A mA mA pF pF VCC = Min, IOH = -4.0mA VCC = Min, IOH = -10A VCC = Min, IOL = 16mA VCC = Min, IOL = -10A VCC = Max, GND VIN VCC I/O = High-Z, GND VO VCC VCC = 5V, VO = 0.5V, TA= 25C VIN = 0V or VCC3,11 f = 25MHz All outputs disabled4 TA = 25C, VCC = 5.0V @ f = 1 MHz 12 6 04-02-052A Table 4. A.C Electrical Characteristics Combinatorial Symbol tPDI tPDX tIA tAL tLC tLO tOD, tOE tOX Over the Operating Range -15/I-15 Min Max 9 15 2 8 1 4 4 15 Parameter 6,12 Unit ns ns ns ns ns ns ns ns Propagation delay Internal (tAL + tLC) Propagation delay External (tIA + tAL +tLC + tLO) Input or I/O pin to array input Array input to LCC LCC input to LCC output10 LCC output to output pin Output Disable, Enable from LCC output7 Output Disable, Enable from input pin7 This device has been designed and tested for the recommended operating conditions. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Figure 15. Combinatorial Timing - Waveforms and Block Diagram 7 04-02-052A Table 5. A.C. Electrical Characteristics Sequential Symbol tSCI tSCX tCOI tCOX tHX tSK tAK tHK tSI tHI tPK tSPI tHPI tSD tHD tSDP tHDP Parameter 6,1 Internal set-up to system clock8 - LCC14 (tAL + tSK + tLC - tCK) Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI) System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC) System-clock to Output Ext. - LCC (tCOI + tLO) Input hold time from system clock - LCC LCC Input set-up to async. clock - LCC Clock at LCC or IOC - LCC output LCC input hold time from system clock - LCC Input set-up to system clock - IOC/INC (tSK - tCK) Input hold time from system clock - IOC/INC (tSK - tCK) Array input to IOC PCLK clock Input set-up to PCLK clock - IOC/INC (tSK-tPK-tIA) Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK) Input set-up to system clock - IOC/INC Sum-D15 (tIA + tAL + tLC + tSK - tCK) Input hold time from system clock - IOC Sum-D Input set-up to PCLK clock (tIA + tAL + tLC + tSK - tpK) - IOC Sum-D Input hold time from PCLK clock - IOC Sum-D System-clock delay to LCC/IOC/INC System-clock low or high pulse width Max. system-clock frequency Int/Int 1/(tSCI + tCOI) Max. system-clock frequency Ext/Int 1/(tSCX + tCOI) Max. system-clock frequency Int/Ext 1/(tSCI + tCOX) Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX) Max. system-clock toggle frequency 1/(tCW + tCW)9 LCC presents/reset to LCC output Input to Global Cell present/reset (tIA + tAL + tPR) Asynch. preset/reset pulse width Input to LCC Reg-Type (RT) LCC Reg-Type to LCC output register change Input to Global Cell register-type change (tRT + tRTV) Asynch. Reg-Type pulse width Power-on reset time for registers in clear state2 17 14 13 -15/I-15 Min Max 5 7 7 11 0 2 1 4 0 4 6 0 6 7 0 7 0 6 6 83.3 71.4 62.5 55.5 83.3 1 11 8 7 1 8 10 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns s tCK tCW fMAX1 fMAX2 fMAX3 fMAX4 fTGL tPR tST tAW tRT tRTV tRTC tRW tRESET 8 04-02-052A Figure 16. Sequential Timing - Waveforms and Block Diagram Notes 1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for periods less than 20ns. 2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at 10% and 90% levels. 3. I/O pins are 0V or VCC. 4. Test one output at a time for a duration of less than 1 sec. 5. Capacitances are tested on a sample basis. 6. Test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 7. tOE is measured from input transition to VREF 0.1V (See test loads at end of Section 6 for VREF value). tOD is measured from input transition to VOH -0.1V or VOL +0.1V. 8. "System-clock" refers to pin 1 or pin 28 high speed clocks. 9. For T or JK registers in toggle (divide by 2) operation only. 10. For combinatorial and async-clock to LCC output delay. 11. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit D-type counter. 12. Test loads are specified in Section 5 of the Data Book. 13. "Async. Clock" refers to the clock from the Sum term (OR gate). 14. The "LCC" term indicates that the timing parameter is applied to the LCC register. The "IOC" term indicates that the timing parameter is applied to the IOC register. The "LCC/IOC" term indicates that the timing parameter is applied to both the LCC and IOC registers. The "LCC/IOC/INC" term indicates that the timing parameter is applied to the LCC,IOC, and INC registers. 15. This refers to the Sum-D gate routed to the IOC register for an additional buried register. 16. The term "input" without any reference to another term refers to an (external) input pin. 17. The parameter tSPI indicates that the PCLK signal to the IOC register is always slower than the data from the pin or input by the absolute value of (tSK -tPK -tIA). This means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. Additionally, the data from the pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at the IOC register. 18. Typical (typ) ICC is measured at TA = 25 C, freq = 25MHZ, VCC = 5V 9 04-02-052A Table 6. Ordering Information Part Number PA7536P-15 PA7536J-15 PA7536S-15 PA7536PI-15 PA7536JI-15 PA7536SI-15 9/15ns I C Speed Temperature Package P28 J28 S28 P28 J28 S28 Figure 17. Part Number Device Suffix PA7536JI-15 Package P = Plastic 600mil DIP S = SOIC J = Plastic (J) Leaded Chip Carrier (PLCC) Speed -15 = 9ns/15ns tpd/tpdx Temperature Range (Blank) = Commercial 0 to 70 C I = Industrial -40 to +85 C 08-16-017A Anachip USA, Inc. 780 Montague Expressway, #201 San Jose, CA 95131 TEL (408) 321-9600 FAX (408) 321-9696 (c)2002 Anachip Corp. Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Anachip. Anachip's products are not authorized for use as critical components in life support devices or systems. (c) Marks bearing or TM are registered trademarks and trademarks of Anachip Corp. Email: sales_usa@anachip.com Website: http://www.anachip.com 10 04-02-052A |
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